Energy-aware dynamic reconfiguration of 3D-stacked L2 cache on DVFS-enabled multi-core동적 전압 / 주파수 조절이 가능한 다중 코어에서 에너지를 고려한 3차원 적층 캐쉬의 동작 모드 결정

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Three-dimensional integrated circuits (3D ICs) have the potential to reduce interconnect length and improve performance. However, high power density of 3D ICs incurs many temperature-related problems, especially leakage power dissipation which exponentially increases with temperature. In this paper, we propose a runtime power management technique for 3D multi-core system. The proposed method minimizes energy consumption of cores, cache, and off-chip memory by integrating dynamic voltage and frequency scaling (DVFS) and dynamic cache reconfiguration (DCR) in a temperature-aware manner without incurring performance penalty. Experimental results based on several benchmark programs: H.264 decoder, ray tracing, and SPEC2000 have shown that the proposed method yields up to 21% reduction in energy consumption compared to the existing method.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2011
Identifier
467826/325007  / 020093417
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2011.2, [ v, 29 p. ]

Keywords

DCR; DVFS; 3D ICs; energy minimization; 에너지 최소화; DCR; DVFS; 3차원 ICs

URI
http://hdl.handle.net/10203/36730
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=467826&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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