Topology synthesis for low power cascaded crossbar switches

Abstract

On-chip communication architecture have a significant impact on the throughput, latency and power consumption of complex SoCs as technology scales to deep submicron. For high clock frequency, global wire delay and pipeline register is most important factors which affect the area, frequency and power consumption of the on-chip communication architecture. The traffic congestion is also important factor, which leads to the degradation of throughput of on-chip communication architecture. We present a topology synthesis method for low power cascaded crossbar switches as backbone network in system-on-chip (SoC). Our method provides a topology of minimum-power crossbar switches ,satisfying given bandwidth, latency, frequency and area constraints. Compared to previous works, the major contribution of our work is the exactness of the solution considering wire delay, traffic congestion and pipeline register insertion. The experimental results shows that the topologies optimized for power consumption with given clock frequency achieves more power reduction (up to 38.0%) over existing method and provides a feasible solution over wide frequency range satisfying given all constraints.