DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Cho, Seong-Hwan | - |
dc.contributor.advisor | 조성환 | - |
dc.contributor.author | Kim, Sung-Jin | - |
dc.contributor.author | 김성진 | - |
dc.date.accessioned | 2011-12-14T01:34:33Z | - |
dc.date.available | 2011-12-14T01:34:33Z | - |
dc.date.issued | 2010 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=419132&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/36580 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ x, 88 p. ] | - |
dc.description.abstract | This thesis proposes a novel time (difference) domain algebraic operation scheme for designing high performance mixed mode systems. Three basic time domain algebraic circuits in order for building a linear system are proposed : time amplifier, time register and time adder. At first, in order to overcome issues that the existing time amplifiers suffer from, two kind of time amplifiers are presented. A variation tolerant and reconfigurable gain time amplifier is proposed in order to achieve large and stable gain. since a NAND gate based ring oscillator replaces the delay lines in the conventional closed loop time amplifier, considerable amount of power and area could be saved. A phase preamplifier added in front of the PFD of the DLL reduces the input phase offset when the DLL is in lock. It is designed and simulated in 90nm CMOS process and the result shows that the time amplifier guarantees 6.3% of gain error over $\plusmn60\degC$ of temperature variation and 15% of supply variation with consuming only 800uW of power. A differential time amplifier also presented to improve linearity of the TA. Through the supply gating of the conventional time amplifier, two amplified time domain information are temporarily stored and efficiently subtracted. As a result, every even order non linearities are suppressed and hence, 16dB improvement of SFDR is achieved. For the second, the ````time addition```` and corresponding circuits are proposed along with general consideration that should be addressed when a new operation is defined. The time adder is implemented by using two unit gain time registers which are based on supply gated inverter delay cell. In addition, a time domain accumulator constructed by the time registers and the time adders is implemented to show the validity of the proposed time domain signal processing scheme. Since the stored information of the proposed time register cannot be read multiple times due to the time domain nature, two pairs of the regis... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | time amplifier | - |
dc.subject | noise shaping | - |
dc.subject | TDC | - |
dc.subject | time domain | - |
dc.subject | time adder | - |
dc.subject | 시간 덧셈기 | - |
dc.subject | 시간 증폭기 | - |
dc.subject | 잡음변조 | - |
dc.subject | TDC | - |
dc.subject | 시간영역 | - |
dc.title | Time domain algebraic operation circuits for high performance mixed-mode systems | - |
dc.title.alternative | 고성능 혼성모드 시스템 설계를 위한 시간 영역 산술 연산 회로 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 419132/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 020083094 | - |
dc.contributor.localauthor | Cho, Seong-Hwan | - |
dc.contributor.localauthor | 조성환 | - |
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