Modeling and analysis of Die-to-Die vertical coupling and RF sensitivity degradation in 3-D IC

Abstract

In this research, die-to-die vertical coupling between clock tree network of digital device and spiral inductor of RF device in three dimension (3D) IC is analyzed. And equivalent circuit model for analysis of vertical coupling between clock tree and spiral inductor is proposed. Analysis and modeling result are verified by measurement results of a designed and fabricated test vehicle which has two stacked dies with clock tree network or a spiral inductor. The proposed model has been successfully verified in the frequency domain from 100MHz to 20GHz. The impedance property of the fabricated test vehicle is thoroughly investigated and analyzed. Vertical coupling effect on RF sensitivity degradation is analyzed. For analysis purpose, it is assumed that DDR3 and Voltage Controlled Oscillator (VCO) of ZigBee transceiver are vertically staked. In order to analyze performance degradation mechanism of VCO, noise coupling path has been separated. Target phase noise and spur specification for proper operation of VCO have been calculated. To achieve proper operation of VCO, vertical shielding method by adding guard shield and noise reduction method by increasing epoxy thickness have been suggested.