DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Hwang, Seung-Ho | - |
dc.contributor.advisor | 황승호 | - |
dc.contributor.author | Han, Tae-Hee | - |
dc.contributor.author | 한태희 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 1999 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=151008&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/36507 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1999, [ [xi], 113 p. ] | - |
dc.description.abstract | Motion estimation is the most compressive step in the video sequence coding, while it requires the most computations. The block matching method has been adopted for the motion estimation in today``s popular video compression standard due to computational simplicity with favorable performance. Both on the algorithmic and architectural level, numerous efforts have been devoted for the cost-effective VLSI realization of the video compressor. In this dissertation, we discuss efficient block matching motion estimation techniques and cost-effective VLSI realization methods considering the trade-off between chip cost and performance demand. We develop a novel hierarchical-search block matching motion estimation algorithm which adaptively selects the initial search level based on the spatial complexity of the matching block. It relies on simple computations of pixel intensity variations in the current macroblock using spatial filters. We demonstrate its effectiveness in two aspects: the performance and the computational cost. A VLSI realization of this algorithm including a half-pel motion estimator and a motion compensation unit is also addressed. The proposed method is highly efficient in enhancing the ratio of the performance improvement to the computation cost. We present efficient VLSI architectures for the two types of array block matching processor. First, for the systolic array type, we develop a robust architecture which is capable of managing the variable size matching block and miscellaneous motion vector prediction modes of MPEG. For enhancing the computation speed and hardware resource utilization, the basic processing element is separated into two functional units: difference unit and accumulation unit. A fast accumulation tree composed of carry-save adders and an ACS (add-compare-select) style comparator are devised to further improve the hardware efficiency. We also develop an area-efficient processing element which is well suited to the search-loca... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | VLSI architecture | - |
dc.subject | Motion estimation techniques | - |
dc.subject | Video compression | - |
dc.subject | 동영상 압축 | - |
dc.subject | 단순 복잡도 | - |
dc.subject | 고성능 | - |
dc.subject | VLSI 구조 | - |
dc.subject | 움직임 추정 기법 | - |
dc.title | Efficient motion estimation techniques and VLSI architectures for video compression | - |
dc.title.alternative | 동영상 압축을 위한 효율적인 움직임 추정 기법과 VLSI 구조에 관한 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 151008/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
dc.identifier.uid | 000945475 | - |
dc.contributor.localauthor | Hwang, Seung-Ho | - |
dc.contributor.localauthor | 황승호 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.