DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Lee, Hee-Chul | - |
dc.contributor.advisor | 이희철 | - |
dc.contributor.author | Kwak, Dong-Hwa | - |
dc.contributor.author | 곽동화 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 1998 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=134752&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/36422 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1998.2, [ v, 158 p. ] | - |
dc.description.abstract | Electrical properties of Pt/BST/Pt MIM capacitor have been investigated. First, a new method for calculating trap density $D_{it} [cm^{-2} \cdot eV^-1]$ with different trap levels in the Pt/BST interface was proposed from current-time curve of the capacitor. Current conduction in DRAM operating region can be well explained by the new model of electron tunneling from the Pt electrode to BST interface trap. This current has apparently linear relationship with applied voltage in current-voltage characteristics when step voltage is applied to the capacitor. The calculated interface trap densities between Pt and BST were in the range of $10^{15} cm^{-2} \cdot eV^{-1} \sim 10^{16} cm^{-2} \cdot eV^{-1}$ which is larger than that of $SiO_2/Si$ interface (usually, in the range of $10^{11} cm^{-2} \cdot eV^{-1} \sim 10^{12} cm^{-2} \cdot eV^{-1}$. Using the data obtained from the current-time curve, the shapes of current-voltage curve with different measuring condition such as delay time were calculated and plotted. The calculated current-voltage characteristic was well coincident with the measured one. A new method was proposed to characterize traps of interfacial BST/Pt layer quantitatively by the hysteresis of capacitance-voltage curve. Interface electron densities trapped at the Pt/$Ba_{0.7} Sr_{0.3} TiO_3$ interface were calculated to be $2 \sim 3 \times 10^{12} cm^{-2}$ independent of BST film thicknesses. Characterization of the interface trap in paraelectric MIM capacitors will be possible using this method. We improved the electrical properties of the MIM capacitor by adopting rapid thermal annealing (RTA) process. The trapped electron density and leakage current density decreased drastically when as-deposited samples were annealed at $650 \,^\circ\!C$ in $O_2$ or $N_2$ ambients for 30s. The effects of the temperature and annealing ambients during RTA on the interface trapped electron density and leakage current density were investigated. The leakage current de... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Tunneling | - |
dc.subject | Pt/BST interface trap | - |
dc.subject | Leakage mechanism | - |
dc.subject | Rapid thermal annealing | - |
dc.subject | 급속 후속 열처리 | - |
dc.subject | 터널링 | - |
dc.subject | 백금/BST 계면 트랩 | - |
dc.subject | 누설 메카니즘 | - |
dc.title | Electrical characterization of interface property in Pt/(Ba, Sr)$TiO_3$/Pt structure for DRAM storage capacitor | - |
dc.title.alternative | DRAM 저장용 캐패시터를 위한 Pt/(Ba,Sr)$TiO_3$/Pt 구조에서의 계면의 전기적 특성 평가 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 134752/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
dc.identifier.uid | 000935014 | - |
dc.contributor.localauthor | Lee, Hee-Chul | - |
dc.contributor.localauthor | 이희철 | - |
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