DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Seong-Dae | - |
dc.contributor.advisor | 김성대 | - |
dc.contributor.author | Jeon, Ki | - |
dc.contributor.author | 전기 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 1995 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=99076&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/36256 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학과, 1995.2, [ v, 114 p. ] | - |
dc.description.abstract | In recent years, digital techniques to achieve dynamic focusing have received a great deal attention in ultrasonic imaging systems. Pipelined sampling-delay focusing (PSDF) is widely used for dynamic focusing, in which many ADC``s, first-in first-out memories (FIFO``s), adders, and sampling clock generation blocks are used. To reduce the complexity of the PSDF system, VLSI implementation for the system is needed, especially for ADC``s, FIFO``s, adders, and sampling clock generators (SCG). However, bulky SCG composed of large memory makes the VLSI implementation difficult. To solve the problem, a focusing delay calculation algorithm has been presented. But the algorithm can not be applied to the focusing using low rate sampling. Therefore, a new algorithm is proposed, which extends midpoint algorithm used in the graphic world to achieve accurate focusing delay in the focusing scheme using low rate sampling techniques. The performance of the new algorithm is compared with that of the previous algorithm and hardware structure to implement the new algorithm is proposed. Also, the word length of the proposed hardware and the round-off error of the new algorithm are analyzed. A beamforming (BF) architecture using the new SCG``s, FIFO``s, and adders is proposed and compared with the previous BF architecture using FIFO``s and adders with respect to FIFO length and memory requirement for the sampling clock generation. A new BF-IC is implemented, which employs the SCG composed of a few digital function units to compute the focusing delay in real time. Mixed mode IC``s including ADC``s, FIFO``s, adders and SCG``s can greatly reduce the focusing system. So, ADC as one cell for the mixed mode IC is needed. To use ADC in the digital focusing using low rate sampling, in this thesis, 10-bit 20 MHz CMOS ADC is designed. This ADC uses a 3-stage pipeline architecture and has the feature of small chip area and high speed. The ADC is composed of wideband high gain op-amps and fas... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | (A) study on new focusing delay calculation algorithm and development of digital beamforming IC and A/D converter | - |
dc.title.alternative | 초음파 영상처리를 위한 새로운 집속지연 계산 알고리즘과 디지탈 집속 IC및 A/D 변환기의 개발에 관한 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 99076/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
dc.identifier.uid | 000865381 | - |
dc.contributor.localauthor | Kim, Seong-Dae | - |
dc.contributor.localauthor | 김성대 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.