A new method for the extraction of device parameters and a solution for the suppression of floating body problem are described for fully-depleted SOI MOSFET. The accurate method to extract the Si film doping concentration and the oxide charge density at both front and back silicon/silicon dioxide interfaces utilizes the current-voltage and capacitance-voltage characteristics of both SOI NMOSFET and PMOSFET which have the same doping concentration. The desired device parameters are extracted from the threshold voltages of the SOI NMOSFET and PMOSFET with proper back surface conditions (accumulation and inversion) and the capacitance-voltage characteristics of the SOI PMOSFET. Device simulations show that the proposed method has less than 10\% error for a wide range of the film doping concentration and the fixed charge densities. Device parameters extracted experimentally from the fabricated test SOI/SIMOX CMOSFET using $n^+$ poly-Si and LOCOS isolation show $Q_{ff}/q, Q_{bf}/q, N_{itb}, and N_A \mbox{as} 4.4\times10^{10}/cm^2, 1.7\times10^{11}/cm^2, 4.5\times10^{10}/eVcm^2,\mbox{and} 7.5\times10^{16}/cm^3$, respectively. The solution to suppress the floating body effect is a newly proposed device design method, which is based on maintaining a high body potential as much as possible. Based on this solution, proper device parameter sets are proposed. Device simulation and experimental results show that SOI NMOSFETs with the proposed device parameter set have improved single latch characteristics by about 1-2V. In order to obtain further improvement in single latch problem and breakdown voltage, $NH_3$ annealing is employed utilizing the results of investigation on the oxide charge characteristics at Si film-to-buried oxide interface according to $NH_3$ annealing condition. The measured results show that $NH_3$ annealed device with low front-gate threshold voltage has improved characteristics by about 2V for single latch effect, about 1V for drain breakdown voltage...