Minimal design of multi-output static CMOS logic circuits using transistor sharing

Abstract

In VLSI design, the design of fast and compact logic modules is very important. Such a goal is tightly coupled with the logic style, circuit design techniques, logic minimization techniques in two-level or multi-level and physical layout techniques. There are many open problems in these area, and still there are also aggressive efforts to enhance the speed and to reduce the power dissipation and chip area in VLSI design. In this thesis, the design techniques of fast and compact logic modules such as carry look-ahead circuit, 3-input full-adder circuit and 8-bit parallel Booth multiplier are proposed, which are based on the transistor sharing schemes in static CMOS complex gates. The transistor sharing schemes are classified largely into two. One is applicable only to either pull-up (PMOS transistors) or pull-down (NMOS transistors) part to implement the given Boolean function and its sub-functions, while the other is simultaneously applicable to pull-up and pull-down part. Although the former method also yields the transistor count less than the conventional Boolean function implementation using the static CMOS complex logic style, it has the problem of heavy imbalance between PMOS and NMOS transistor count due to the reduction of transistor count in either pull-up part only or pull-down part only, which yields the problem of inefficient static CMOS layout. To solve the problem, the logic redundancy technique which inserts redundant transistors into static CMOS complex gate, and the functionality sharing technique based on the mutual replacement between the generated sub-functions by the local graph dualities, i.e., the inverse Boolean representations between each other, are introduced. These two schemes enable PMOS and NMOS transistors to be shared simultaneously for the implementation of the given Boolean function and its sub-functions, which gives a more balanced reduction of transistor count for an efficient static CMOS layout. The logic redundancy techniqu...