For system-level simulation of a complex system-on-chip design, multiple hardware simulators and emulators can be combined to work together. The simulation performance in this case is often limited by the communication overhead between simulators and emulators. To improve simulation performance in this heterogeneous simulation environment, this thesis proposes three novel methods: the first method is simulator scheduling based on the prediction of communication between simulators, the second is distributed communication modeling, and the third is a unified simulation platform for hardware and software using SystemC single kernel. To reduce the amount of communication between the simulators the first method finds time interval during which there are no transactions among simulators through a dynamic prediction of transaction occurrence time for both software and hardware models. The proposed simulator scheduling algorithm allows the simulator to work alone without interaction with others when there is no transaction. Unlike existing multiprocessors simulation tools that use a centralized server, which manages clocks for all processor models and inter-processor communication, the second method separates the synchronization and communication and distributes the large portion of the tasks to each simulation model. The amount of synchronization is reduced, and the message passing among the processor models through time-consuming Inter-Process Communication (IPC) is removed. The unified simulation platform in the third method provides fast and accurate high-level co-simulation using SystemC for hardware and legacy C for software. Automatically modified legacy C synchronizes with SystemC clock events, and communicates with other modules through IO (Input/Output) variables and transaction level bus models. A generic multithread scheduler and APIs (Application Programming Interface) are supported for multithreaded real-time applications. In addition, this thesis introd...