DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kyung, Chong-Min | - |
dc.contributor.advisor | 경종민 | - |
dc.contributor.author | Lee, Jae-Gon | - |
dc.contributor.author | 이재곤 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2006 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=254419&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/36049 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2006.2, [ vii, 88 p. ] | - |
dc.description.abstract | This paper presents a scheme called PrePack for suppressing the channel traffic between simulator and accelerator in the accelerator-based hardware/software co-emulation where the accelerator models some RTL sub-blocks while the simulator runs transaction-level model of the remaining part of the Design Under Verification (DUV). With conventional simulation accelerator, a cycle consisting of a pair of evaluations of simulator and accelerator occurs at every valid simulation time, which results in poor simulation performance due to the overhead of simulator-accelerator channel access often accounting for more than 99% of total channel traffic time. (Total channel traffic time consists of channel access time for arbitration/protocol exchange and pure data/signal transmission time.) The overhead due to channel access can be reduced by merging as many channel transactions on the channel as possible into a single burst traffic, which is achieved in this paper by `prediction and rollback.`` In the proposed `prediction and rollback`` scheme, one of the two verification do-mains, i.e., software simulation and hardware acceleration, leads the other while the leading domain predicts the states of the lagging domain. Therefore, the evaluation of simulator and accelerator no longer need to alternate at every simulation cycle. Under ideal condition with 100% prediction accuracy, PrePack has shown a 15x speedup compared to the conventional scheme. When applied to AES and JPEG example systems, PrePack showed performance gain of 8.7 and 2.9, respectively. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | SystemC | - |
dc.subject | TLM | - |
dc.subject | transaction-level modeling | - |
dc.subject | Simulation acceleration | - |
dc.subject | system-level modeling | - |
dc.subject | SoC | - |
dc.subject | 시스템 수준 모델링 | - |
dc.subject | 시스템 | - |
dc.subject | 트랜잭션 레벨 모델링 | - |
dc.subject | 시뮬레이션 가속 | - |
dc.subject | SoC | - |
dc.title | Simulation acceleration of transaction-level SoC design with RTL sub-blocks | - |
dc.title.alternative | 레지스터 전송 수준 하위 블록을 포함한 트랜잭션 수준 SoC 디자인의 시뮬레이션 가속 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 254419/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 020005243 | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.localauthor | 경종민 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.