Modeling of on-chip interconnects inductance and analysis of substrate coupling in cmos integrated circuits

Abstract

As semiconductor technology scales, on-chip parasitic effects from interconnects and lossy substrate are becoming major concerns in integrated circuit design. Increase in interconnect delay and crosstalk together with reduction of threshold voltage of transistors have significantly worsened design margins. Especially, with higher clock frequencies and longer interconnect length, inductance of the wires can no longer be ignored in modern VLSI circuits. Inductive signal overshoots and ringing effects result in high gate input voltages which cause thin-oxide reliability problem and circuit malfunctioning. Mutual inductance degrades signal integrity by injecting inductive noise on victim lines in multiple bus structure. Therefore, accurate understanding and modeling of the parasitic parameters of interconnects have become more critical than ever. With the improvement of the performance of CMOS device, analog and RF circuits are willing to be merged with digital blocks on a single silicon substrate. Implementation of digital and analog circuits on a single substrate causes severe parasitic crosstalk between two blocks through lossy substrate. This dissertation focuses on two major coupling causes in CMOS integrated circuit, interconnects inductance and silicon substrate. A loop-based inductance model is proposed and substrate coupling is characterized by on-wafer measurement. Two interesting topics, the effects of off-diagonal terms in resistance matrix and comparative study of de-embedding methods, are also studied. In the first part of this dissertation, an efficient loop inductance extraction and modeling methodology including mutual inductance for high-speed on-chip interconnects is proposed. This model is based on physical layout considerations and the phenomenon of current distribution in multiple returns, and predicts well the self and mutual inductances within a wide frequency range without any fitting algorithm and optimization process. It can be generated ...