Design and implementation of 3D graphics rendering engine in 2D array embedded memory logic CMOS

Abstract

Energy efficient high performance rendering architecture is proposed and its silicon verification is successfully demonstrated using 0.35μmEML technology. The 11.1M polygon/sec drawing speed and 7.1GB/s memory access bandwidth are achieved @ 100Mhz, 3.3V with 2.4W power consumption. It achieves energy efficient pixel parallel rendering operation with about 300Kpixel/mW rendering performance. This result shows 1.8~3.0 times power-energy efficiency compared with the other EML based rendering chips. The main features are 2-dimensional hierarchical octet tree (2D-HOT) array architecture and bandwidth amplification (BA). The following features are cooperates together. Embedded network interface schemes provide the energy efficient bus transaction. The virtual page mapping and polygon level parallel rendering enhance the utilization of 2D-HOT array. Asynchronous propagation for shading operation provides fast and low power interpolation. The low power bit-wise read-compare-write (RCW) scheme reduces DRAM power consumption to 78.2%~103.5% of the conventional schemes according to the data access patterns. For fast and accurate embedded DRAM (eDRAM) power-energy estimation, the signal swing-based analytical (SSBA) eDRAM power-energy model is proposed. The system-level eDRAM power-energy estimation methodology, which combines the SSBA model and the system-level memory access statistics, is used to investigate the power-energy characteristics of various rendering architectures.