Orthogonal tRAM and bank-driven embedded memory architecture for two dimensional signal processing이차원 신호처리를 위한 직교형 티램과 향상된 뱅크구조를 가지는 임베디드 메모리에 대한 연구

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 484
  • Download : 0
The embedded memories in the embedded system are prevalent with advances in the VLSI technology and the associated design paradigms have shifted. In this thesis, embedded memory architectures for two-dimensional signal processing have been proposed for efficient data flow in the I/O bounded problems and optimized under the off-/on-chip memory bandwidth and one-chip criterion. The figure of merits will be addressed through the intrinsic embedded memory architecture and the usage in the application such as Motion Estimation (ME). Unlike the off-chip memory increasing the peak performance, embedded memories can be exploited to suit specific applications for the two-dimensional signal processing where overhead clocks are induced by the architectural hazards in mismatch between storage components and Processing Elements (PEs). By applying an architecture driven voltage scale, we analyze the effects of the overhead clocks in power consumptions. For reducing the power consumed by these overhead clocks and maximizing the useful data transfer rate, we will propose two approaches using the asymmetric/complementary embedded memory banks and the orthogonal transpose-RAM cell array. The prototype processor with asymmetric, complementary embedded memory banks has been fabricated with 0.6um standard CMOS technology with 1-poly and 3-metal, where several techniques are employed to reduce the silicon area occupied by the memory block and room for the metal tracks used in PEs. The results show that power saving is improved by using complementary access types of memory banks and amounts to 27.3% compared to an identical design without the proposed enhancements when the Full-search Block Matching Algorithm (FBMA) is applied for the CCIR-601 format. The proposed asymmetric, complementary embedded memory banks make an ME processor efficient and optimal for interest wide range in spite of the area-overhead. The implemented chip operates at 2.5mW/MHz and 3.3V supply voltage. Accordi...
Advisors
Lee, Kwy-Roresearcher이귀로researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2001
Identifier
169561/325007 / 000975026
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2001.8, [ viii, 115 p ]

Keywords

Low Power; Orthogonal Memory Reading; Two-dimensional Signal processing; Embedded Memory; High Efficiency; 고 효율; 저 전력; 직교형 메모리 읽기; 이차원 신호 처리; 임베디드 메모리

URI
http://hdl.handle.net/10203/35954
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=169561&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0