Design of low-noise RF synthesizer for wireless transceiver using ring oscillator링 발진기를 이용한 이동 통신용 저 잡음 고 주파수 합성기의 설계

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dc.contributor.advisorKim, Beom-Sup-
dc.contributor.advisor김범섭-
dc.contributor.authorPark, Chan-Hong-
dc.contributor.author박찬홍-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2001-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=169556&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35953-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2001.8, [ ix, 115 p. ]-
dc.description.abstractFirstly, this paper describes a design methodology for low-noise ring-type CMOS RF VCO (voltage-controlled oscillator). To reduce the VCO phase noise, a noble delay cell with full switching and fast slewing is proposed. Dual delay path technique is also used in routing the delay cells to achieve high oscillation frequency, and to get a wide tuning range. By using the delay cell and the routing method, a 900 MHz VCO is fabricated in a 0.6 mm CMOS technology. The VCO operates at 750MHz to 1.2 GHz and the tuning range is as large as 50 %. The measured results of the phase noise are -101 dBc/Hz at 100 kHz offset, and -117 dBc/Hz at 600 kHz offset from the carrier frequency. This value is comparable to that of LC based integrated oscillators. Secondly, a noble edge-combing method to implement a fractional-N frequency synthesizer is proposed. By combining the edges of the multi-phase signals generated by the ring-type VCO, fractional frequency dividing is directly performed without dithering or phase compensation causing fractional spurs or quantization noise. The fractional divider maximizes the loop bandwidth of the PLL, to reduce the effect of the close-in phase noise of the VCO on overall phase noise. Finally, this paper describes a self-calibration method to compensate the delay mismatches between the delay cells in a ring oscillator. The self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the I/Q phase error. It also reduces the fractional spurs found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the I/Q oscillating signals can be picked from the multi-phase signals with less than 0.2℃ phase offset. The edge-combing frequency synthesizer PLL including the self-calibration circuit is implemented in 0.35㎛ CMOS technology. It operates from 1.7 GHz to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100 kHz offset from the carri...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectRF VCO-
dc.subjectRF synthesizer-
dc.subjectRF transceiver-
dc.subject이동 통신-
dc.subject발진기-
dc.subject주파수 합성기-
dc.titleDesign of low-noise RF synthesizer for wireless transceiver using ring oscillator-
dc.title.alternative링 발진기를 이용한 이동 통신용 저 잡음 고 주파수 합성기의 설계-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN169556/325007-
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid000965166-
dc.contributor.localauthorKim, Beom-Sup-
dc.contributor.localauthor김범섭-
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EE-Theses_Ph.D.(박사논문)
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