Substrare fed threshold logic

Abstract

A new structure, called Substrate Fed Threshold Logic (SFTL), is proposed for the implementation of multivalued logic (MVL). SFTL has the same circuit diagram as Integrated Injection Logic ($I^2L$). In SFTL, as threshold current is supplied from the $p^+$-substrate to the top p-region through the windows in the $n^+$-buried layer, and quantized by the number of the injection windows in the buried layer, the error of the threshold level can be substantially reduced. The feasibility of SFTL to MVL has been discussed theoretically and experimentally. The results show that four-valued threshold logic is possible with the proposed structure. A specially designed SFTL process has been used to obtain high upward current gain and high packing density. In the process two self alignments have been achieved by using a single layer of nitride layer. With the SFTL structure, normal binary logic operation has been confirmed by a 23-stage ring oscillator with a minimum delay time of 41ns. A binary full adder whose internal operation is performed by four-valued. Threshold logic has been fabricated and tested by interconnecting the pads of each cell externally. The delay times of the experimental circuits operating with 10 μA per injection window have been measured as 5 μs for the sum and 1 μs for the carry.