Parametric investigation of zone melting recrystallization of polysilicon and threshold voltage model for thin SOI MOSFET

Abstract

Solutions to several major problems in ZMR such as agglomeration of polysilicon, slips and local substrate melting in recrystallization process are described. Experiments are performed with varying polysilicon thickness and capping oxide thickness. In order to introduce nitrogen at the capping layer-to-polysilicon and polysilicon-to-buried layer, the SOI sample is annealed before recrystallization process. The agglomeration of polysilicon is eliminated when the SOI sample is annealed at 1100℃ in $NH_3$ ambient for three hours. In order to prevent slips and local substrate melting the back surface of silicon substrate is sandblasted. As a result, the slips and substrate melting are removed when the roughness of back surface is about 20㎛. The subboundary spacing increases with increasing polysilicon thickness and the uniformity of recrystallized SOI film thickness improves with increasing capping oxide thickness, thereby the quality of recrystalized SOI film is improved. When the polysilicon thickness is about 1.0㎛ and the capping oxide thickness is 2.5㎛, the thickness variation of recrystallized SOI film is about ±20nm. SOI n-channel MOSFETs are fabricated to investigate the quality of the recrystallized SOI film. As a result, the recrystallized SOI film is shown to be good enough to fabricate devices. An analytical threshold voltage and subthreshold models of a long channel SOI MOSFET are proposed. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Therefore the model is self-consistent with the measurement scheme. Numerical simulations show good agreement with the analytical model for wide variations of parameters such as film doping concentration, front gate oxide thickness and front and back interface charge density, and the error is less than 3%.