High performance low power real-time multi-object recognition processor with visual perception engine시각 인식 가속기를 집적한 고성능 저전력 실시간 다중 물체 인식 프로세서

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dc.contributor.advisorYoo, Hoi-Jun-
dc.contributor.advisor유회준-
dc.contributor.authorKim, Joo-Young-
dc.contributor.author김주영-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2010-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=455214&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35599-
dc.description학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2010.02, [ x, 153p. ]-
dc.description.abstractA 201.4GOPS real-time multi-core processor is proposed to minimize the energy consumption per frame for multi-object recognition. In algorithm level, we devise the visual perception based object recognition model that extracts the regions-of-interest (ROIs) of objects first and then performs detail object recognition processing consisting of image processing and database matching. By reducing the effective processing area by 3 times, the proposed object recognition algorithm largely improves energy efficiency. To implement the proposed visual perception based object recognition in energy efficient way, we propose the attention controlled multi-core architecture consisting of two IP layers having different roles. The attention/control IPs estimate the global workloads of overall image, e.g., the number of ROI tiles, and control multiple processing cores based on them for efficient image processing. In this architecture, we find out the energy efficient solutions for the four issues: multi-core organization, ROI processing model, ROI task scheduling, and IP communication. Putting the solutions together, the proposed architecture improves 3.7 times energy efficiency from the conventional multi-core architecture. After that, we tailor the proposed architecture to three-stage pipelined architecture to maximize the throughput of object recognition. In addition, we also design an application-specific network-on-chip to resolve the data communication problems under the target object recognition traffic. For chip implementation, we designed three kinds of IP blocks for three stages of the proposed object recognition, visual perception, main image processing, and post database matching. Especially, in the design of visual perception, we exploit bio-inspired neural networks and fuzzy logic circuits for human-like ROI estimation. We employ multiple SIMD processors and vector matching accelerator for main image processing and post database matching, respectively. In overa...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectNetwor-on-Chip-
dc.subjectMulti-core-
dc.subjectObject recognition-
dc.subjectVisual perception-
dc.subjectVision system-
dc.subject비전 시스템-
dc.subject네트워크 온 칩-
dc.subject멀티 코어-
dc.subject물체 인식-
dc.subject시각 인식-
dc.titleHigh performance low power real-time multi-object recognition processor with visual perception engine-
dc.title.alternative시각 인식 가속기를 집적한 고성능 저전력 실시간 다중 물체 인식 프로세서-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN455214/325007 -
dc.description.department한국과학기술원 : 전기 및 전자공학과, -
dc.identifier.uid020075036-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.localauthor유회준-
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EE-Theses_Ph.D.(박사논문)
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