DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Joung-Ho | - |
dc.contributor.advisor | 김정호 | - |
dc.contributor.author | Shim, Jong-Joo | - |
dc.contributor.author | 심종주 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2010 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=418820&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35591 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ xiv, 114 p. ] | - |
dc.description.abstract | In this research, a new adaptive on-chip equivalent series resistance (ESR) controller scheme in power distribution network (PDN) is proposed in order to reduce the on-chip simultaneous switching noise (SSN). The proposed on-chip ESR controller scheme has an SSN monitoring block, an ESR controller digital block and an on-chip PDN block with the proposed digitally controllable series resistors. The proposed adaptive on-chip ESR is adaptively changed to reduce the on-chip SSN by using the proposed adaptive on-chip ESR controller scheme. The test chip with the test on-chip PDN, the on-chip SSN monitoring block and the digital control block is designed in a 65 nm HYNIX CMOS process and a $0.18\microm$ TSMC CMOS process. The total sizes of the test chips occupy the areas of $3000 \microm$ by $2100\microm$ and $2000 \microm$ by $1250 \microm$, respectively. As changing the on-chip controllable ESR value, it is analyzed how the peak-to-peak SSN at the on-chip PDN is changed, by Fourier analysis. Also, the optimum controllable ESR value is obtained theoretically, as changing the pulse width and rising/falling time of the switching noise current, the off-chip inductance and on-chip capacitance. Comparing with the conventional PDN (without proposed scheme), not only peak-to-peak SSN but also switching power consumed in the PDN is able to be reduced by the proposed adaptive on-chip ESR controller scheme. Also, the applicable frequency range is analyzed for the proposed adaptive on-chip ESR controller scheme, in this research. Finally, the proposed adaptive on-chip ESR controller scheme is successfully verified through the SSN measurements and simulated results in time domain. It is confirmed that the on-chip resonance, caused by the off-chip inductance and the on-chip capacitance of on-chip decoupling capacitor, is reduced by changing the proposed digitally controllable ESR of the on-chip decoupling capacitor. Furthermore, it is proved that the on-chip SSN is reduced... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Adaptive Control | - |
dc.subject | Equivalent Series Resistance | - |
dc.subject | Power Distribution Network | - |
dc.subject | Simultaneous Switching Noise | - |
dc.subject | Noise Reduction | - |
dc.subject | 잡음 감소 | - |
dc.subject | 적응형 제어 | - |
dc.subject | 등가 직렬 저항 | - |
dc.subject | 전력 분배 망 | - |
dc.subject | 동시 스위칭 잡음 | - |
dc.title | (An) Adaptive on-chip equivalent series resistance controller scheme in power distribution network for simultaneous switching noise reduction | - |
dc.title.alternative | 동시 스위칭 잡음 감소를 위한 전력 분배 망 내의 적응형 온-칩 등가 직렬 저항 조절 회로 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 418820/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 020055089 | - |
dc.contributor.localauthor | Kim, Joung-Ho | - |
dc.contributor.localauthor | 김정호 | - |
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