Modeling and analysis of chip-package-pcb hierarchical power distribution network based on segmentation method

Abstract

In this research, a new modeling method for the estimation of impedance properties in a chip-package-PCB hierarchical PDN is proposed. The key approach of the proposed modeling method is to decompose the chip-package-PCB hierarchical PDN into independent structures and calculate the impedance properties of the decomposed structures independently. After decomposition and independent estimations, the impedance properties of the total structure are induced by using a segmentation method. In order to calculate the independent structures in the chip-package-PCB hierarchical PDN, five kinds of modeling approaches are introduced. First, a modeling method to estimate impedance of a grid chip level PDN is proposed. Second, a resonant cavity model is used to represent the PDN impedance at a package level and PCB level. Third, we propose a modeling procedure to add the effect of the interlevel electromagnetic coupling between a package level and PCB level PDN. Fourth, a modeling procedure to include the fringing field effect and a new parameter of AWFF (additional width for fringing field) are introduced. Finally, lumped circuit models for the interconnections such as balls, vias and bond-wires are used as a pi-type network composed of inductors and capacitors. In order to verify the proposed modeling method, a test vehicle by combining two chip level PDNs, two package level PDNs and a PCB level PDN has been fabricated. The proposed modeling method has been successfully verified by compared to experiments in the frequency domain from 100MHz to 20GHz. The impedance property of the chip-package-PCB hierarchical PDN is thoroughly investigated and analyzed. Especially, a mode resonance in the chip is newly observed, investigated and proposed. New analysis methods and equations for the calculation of mode resonant frequency in a grid chip level PDN are also proposed and verified.