(A) digital-intensive RF sampling receiver for multi-mode multi-band applications = 다중모드 다중대역을 지원하는 디지털 RF 샘플링 수신기

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This thesis introduces a digital-intensive RF sampling receiver which consists of a low-noise amplifier employing an on-chip transformer, a time-interleaved RF VCO-based analog to digital converter, and a low-jitter clock generator with an automatic frequency calibration. In addition, in order to solve the problems of the proposed clock generator, an area-efficient LC-VCO based clock generator and an injection-locked multi-modulus frequency divider are also demonstrated in the silicon. A highly linear and low noise RF front-end circuits for 2.4 GHz low-IF receiver is also implemented. Each of the chapter presented in this thesis covers a specific block associated with the digital-intensive RF sampling receiver. Firstly, this thesis presents an ultra-low jitter clock generator that employs a novel automatic frequency calibration (AFC) technique is presented. In order to achieve low jitter, the clock generator uses an LC-VCO with the 5-bit digitally controlled capacitor array. The capacitor array of the LC-VCO is controlled by a novel AFC technique that uses time-to-voltage conversion (TVC) scheme for the fast calibration time. The proposed AFC performs binary search to reduce the numbers of the frequency comparison and fine search to select an optimum tuning curve for accuracy of the frequency calibration. The clock output is taken from the output of a multi-modulus divider, which induces small variation in the loop bandwidth of the phase locked loop (PLL). A prototype chip implemented in 0.13 $\mum$ CMOS process achieves 480 MHz to 1 GHz of output frequency while consuming 22 mW from a 1.2 V supply. The measured rms jitter and frequency calibration time of the proposed clock generator are 940 fs at 600 MHz and 350 ns, respectively. These numbers are the fastest calibration time and one of the lowest jitter that have been reported in a clock generator. Secondly, an ultra low-jitter clock generator that employs an area-efficient LC-VCO is presented. In order ...
Advisors
Cho, Seong-Hwanresearcher조성환researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
418687/325007  / 020037509
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ xiii, 151 p. ]

Keywords

아날로그 디지털 컨버터; 수신기; 디지털 수신기; 라디오 프리퀀시; 저 잡음 증폭기; RF; Receiver; LNA; RF ADC; digital RX

URI
http://hdl.handle.net/10203/35559
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=418687&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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