Design and implementation of network-on-chip based multi-core processor for object recognition = 물체인식을 위한 네트워크 온 칩 기반의 다수코어 프로세서의 설계 및 구현

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For mobile intelligent robots, object recognition is an essential function to realize intelligent actions such as autonomous navigation. In recent years, an object recognition based on scale invariant feature transform (SIFT) is most widely adopted for various mobile robots since it is robust to scale, lighting, and orientation changes of objects. To realize the SIFT object recognition on the mobile robots, providing vast computation power with low power consumption is a significant issue. The SIFT requires enormous amount of computation for repeated image filter operation on a large number of pixels, and low power consumption is also important due to limited power supply of mobile robots. To my best knowledge, there had been no processor implementation adequate to support object recognition on mobile robots prior to this work. The previous processors only provide insufficient performance with low power consumption or high performance with impractical power consumption. In this work, high performance and power efficient object recognition processor is implemented using 0.18um standard CMOS process technology. Based on the analysis of the target application which is the SIFT object recognition in this work, power efficient design of high performance processor is achieved. To answer the high performance requirement of the SIFT object recognition, a multi-core processor architecture comprising ten processing elements and eight special purpose memories is proposed. The architecture of the proposed processor is devised regarding the flexible mapping of various stream processing models which are inherent in various image processing applications including the object recognition. As for hardware accelerators, decisions on addition of SIMD instruction for each PE and design of visual image processing (VIP) memory are made by observing the two most demanding tasks of the SIFT object recognition. The VIP memory replaces local maxim pixel search operation, which takes 41...
Yoo, Hoi-Junresearcher유회준researcher
한국과학기술원 : 전기및전자공학전공,
Issue Date
309323/325007  / 020037075

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ 97 p. ]


Network-on-Chip; object recognition; multi-core processor; 네크워크 온 칩; 물체인식; 다수코어 프로세서; Network-on-Chip; object recognition; multi-core processor; 네크워크 온 칩; 물체인식; 다수코어 프로세서

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