Design and implementation of low phase noise VCO for power aware frequency synthesizer전력 소비 적응형 주파수 합성기에 적합한 저잡음 전압 제어 발진기의 설계와 구현

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 526
  • Download : 0
DC FieldValueLanguage
dc.contributor.advisorCho, Seong-Hwan-
dc.contributor.advisor조성환-
dc.contributor.authorKu, Yeon-Woo-
dc.contributor.author구연우-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2008-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=303620&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35472-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2008. 8., [ viii, 86 p. ]-
dc.description.abstractIn this dissertation, the concept of power aware optimization is proposed for designing multi-standard frequency synthesizer based on phase-locked loop in a single chip. To prove the proposed concept, a multi-standard frequency synthesizer based on PLL (FS-PLL) is designed for Bluetooth, Zigbee (802.15.4), and WLAN (802.11b) at 2.4 GHz ISM band as a test-bed. Simulated results show that specifications for each standard are satisfied without any degradation of figure of merit (FOM) such as power consumption and silicon area. Each building block of the proposed FS-PLL is designed as follows. A fully differential charge pump is designed having small UP/DN current mismatches and its current is controlled by the constraint of pass-band noise specification. A modified dual path loop filter is proposed to reduce the component size by almost twenty times compared to counterparts of the conventional structure. This alleviates silicon area concerns helping us to easily integrate a loop filter in a single chip. To ensure the wide variation of phase noise, the power consumption of VCO is controlled by a MOS switched tail current source from 1 mW to 18 mW corresponding to 13 dB phase noise difference. Thus, the designed VCO maintains almost constant FOM over the range of its power consumption. That is the ultimate goal of this thesis so-called the concept of power aware optimization. In addition, it is found that an optimum current mirror ratio between the VCO core and the bias circuit exists for low phase noise under a fixed current budget. Contrary to the conventional beliefs that current in the VCO must be maximized for low phase noise, it is shown that the designers must be careful of the current allocation in current mirror to minimize the phase noise. The fabricated VCO has 3~4 dB higher FOM compared to the um-optimized VCO. This is another useful optimization method for achieving a low phase noise VCO in a given current budget. In particular, for narrow channel...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectVCO-
dc.subjectpower aware-
dc.subjectfrequency synthesizer-
dc.subjectphase noise-
dc.subjectmulti-standards-
dc.subject전압 제어 발진기-
dc.subject전력 소비 적응-
dc.subject주파수 합성기-
dc.subject위상 잡음-
dc.subject다중 표준-
dc.subjectVCO-
dc.subjectpower aware-
dc.subjectfrequency synthesizer-
dc.subjectphase noise-
dc.subjectmulti-standards-
dc.subject전압 제어 발진기-
dc.subject전력 소비 적응-
dc.subject주파수 합성기-
dc.subject위상 잡음-
dc.subject다중 표준-
dc.titleDesign and implementation of low phase noise VCO for power aware frequency synthesizer-
dc.title.alternative전력 소비 적응형 주파수 합성기에 적합한 저잡음 전압 제어 발진기의 설계와 구현-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN303620/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020015017-
dc.contributor.localauthorCho, Seong-Hwan-
dc.contributor.localauthor조성환-
Appears in Collection
EE-Theses_Ph.D.(박사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0