(A) multithread expanded VLIW vertex processor with vertex caches정점 캐쉬와 다중 쓰레드 확장 VLIW 구조를 가지는 정점 프로세서

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 433
  • Download : 0
DC FieldValueLanguage
dc.contributor.advisorLee-Sup Kim-
dc.contributor.advisor김이섭-
dc.contributor.authorChanghyo Yu-
dc.contributor.author유창효-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2007-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=301334&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35469-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2007.8, [ viii, 97 p. ]-
dc.description.abstractEarly implementations of the embedded mobile 3-D graphics processor mainly focused on core area and power dissipation to provide graphics functions into a SoC platform within a limited area and a power budget. After that, the demand on rapidly increasing multimedia applications, such as mobile cell-phone, PDA, and so on, initiates to develop the processing performance of the graphics processor while maintaining its power dissipation suitable for mobile systems. Recently, embedded 3-D graphics processors continuously increase their functionality as well as the processing performance and reduce the power dissipation to achieve more realism on the power or energy-limited mobile systems. In this thesis, an energy efficient floating-point vertex processor is proposed making use of not only low-power techniques but also graphics-specific characteristics to acquire higher performance as well as better power efficiency for the mobile graphics environment. It supports the up-to-dated OpenGL ES 2.0 and a high-end standard, Vertex Shader 3.0, which include the advanced functions, such as flow controls and vertex texturing. The datapath is an efficient combination of functional units for the 3-D graphics vertex processor while providing sufficient operands with limited read and write-ports to reduce the power dissipation and the excessive number of registers ports in the VLIW datapath. In the proposed datapath, a power management unit is implemented to control the state of the whole processor parts with the operand isolation and clock gating methods as well as a processor’s state-related sleep mode in on-chip memories. To reduce the bandwidth between hosts and graphics processors and to improve the vertex processing performance, vertex caches are also implemented with an optimized configuration. To give more programmability and efficiency, a vertex texture fetcher with four sampler units is implemented into the datapath, which is the first implementation on the embedde...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subject3D Graphics-
dc.subjectGeometry Engine-
dc.subjectVertex Processor-
dc.subjectVertex Shader-
dc.subjectVertex Cache-
dc.subjectVLIW-
dc.subject삼차원 가속기-
dc.subject기하연산 프로세서-
dc.subject정점 프로세서-
dc.subject정점 캐쉬-
dc.subject3D Graphics-
dc.subjectGeometry Engine-
dc.subjectVertex Processor-
dc.subjectVertex Shader-
dc.subjectVertex Cache-
dc.subjectVLIW-
dc.subject삼차원 가속기-
dc.subject기하연산 프로세서-
dc.subject정점 프로세서-
dc.subject정점 캐쉬-
dc.title(A) multithread expanded VLIW vertex processor with vertex caches-
dc.title.alternative정점 캐쉬와 다중 쓰레드 확장 VLIW 구조를 가지는 정점 프로세서-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN301334/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020035184-
dc.contributor.localauthorLee-Sup Kim-
dc.contributor.localauthor김이섭-
Appears in Collection
EE-Theses_Ph.D.(박사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0