Design of robust memory with embedded RISC

Abstract

An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nano-technology memory. The proposed scheme, SAC is composed of sensing blocks, analysis blocks and control blocks. Sensing is to sense the internal status inside the memory device by on-chip sensors. Analysis is to analyze the data from sensors based on pre-defined rules. Control is to control internal parameters such as power supply voltage, timing or duration of control signals for stable and desired operation. It is a kind of closed-loop control systems. Two applications are shown to prove the effectiveness of the SAC scheme. The first application is SRAM with the SAC scheme. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area and low voltage level of wordline are controlled. A 512-kb test SRAM chip fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9 %, and the standard deviation decreases by 58 %. The second application is PRAM with the SAC scheme. In PRAM case, more powerful analysis and control are required because of higher complexity and uncertainty than the first case. The uRAMP, an 8-bit RISC processor, is embedded for analysis and control. The uRAMP gives not only analysis and control for the SAC scheme, but also high performance such as a 100-Mb/s/pin read and write throughput. A 4-Mb test PRAM chip with uRAMP was fabricated in a 90-nm diode-switch PRAM cell process. The uRAMP controls the timing, pulse width and voltage of all control signals for PRAM core according to the algorithm saved in code memory. Test result shows that the distributions of GST cell resistances are improved remarkably. The margin window between the resistance distributions...