Design and characterization of low-power RTD/HBT digital ICs for high-speed transceivers초고속 Transceiver를 위한 저전력 공명 터널링 다이오드/이종접합 바이폴라 트랜지스터 디지털 회로의 설계 및 특성 분석

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dc.contributor.advisorYang, Kyoung-hoon-
dc.contributor.advisor양경훈-
dc.contributor.authorKim, Tae-ho-
dc.contributor.author김태호-
dc.date.accessioned2011-12-14-
dc.date.available2011-12-14-
dc.date.issued2007-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=301331&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/35466-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2007.2, [ xiv, 132 p. ]-
dc.description.abstractIn this work, high-speed RTD/HBT NDR digital ICs such as a D-flip flop, a static frequency divider, and a 2:1 multiplexer are proposed for high-speed and low-power operation for the first time. A Current Mode Logic (CML) type RTD/HBT MOnostable-BIstable transition Logic Element (MOBILE) IC with complementary outputs is proposed, which can simplify logic designs on the basis of complementary logic operation. By using the CML-type current modulator in the MOBILE IC, both the non-inverted and inverted outputs are simultaneously generated with a single input signal. The CML-type MOBILE IC with complementary outputs has been fabricated using an InP-based RTD/HBT technology, and the operation of the fabricated circuit has been confirmed up to 10 Gb/s as a MOBILE with the complementary outputs. Moreover, the operation of a non-return-to-zero (NRZ) D-flip flop with a single output, integrated with a conventional SET/RESET latch using the CML-type complementary MOBILE IC has been confirmed up to 8 Gb/s with a low-power consumption of 86 mW. Also, a new CML-type SET/RESET latch has been proposed. By using the CML-type configuration in the proposed SET/RESET latch, the high-speed operation and the compatibility with the conventional ECL interface have been achieved. The basic operation of the proposed circuit has been confirmed through the DC transfer characteristic measurements. Also, the operation of the fabricated circuit with common-emitter output buffers has been demonstrated up to 10 Gb/s with low power consumption of 23 mW. A low-power RTD/HBT MOBILE-based D-flip flop is proposed and implemented using an InP-based monolithic RTD/HBT IC technology. The proposed MOBILE-based D-flip flop consists of a current mode logic (CML) type MOBILE core with complementary outputs and a CML-type SET/RESET latch, and has several advantages of the reduced device count and low-power consumption over the conventional D-flip flop based on a master/slave configuration. The o...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectRTD-
dc.subjectHBT-
dc.subjectHigh-Speed Digital ICs-
dc.subjectNDR-
dc.subjectMOBILE-
dc.subject공명터널링 다이오드-
dc.subject이종접합 바이폴라 트랜지스터-
dc.subject초고속 디지탈 회로-
dc.subjectNDR-
dc.subjectMOBILE-
dc.subjectRTD-
dc.subjectHBT-
dc.subjectHigh-Speed Digital ICs-
dc.subjectNDR-
dc.subjectMOBILE-
dc.subject공명터널링 다이오드-
dc.subject이종접합 바이폴라 트랜지스터-
dc.subject초고속 디지탈 회로-
dc.subjectNDR-
dc.subjectMOBILE-
dc.titleDesign and characterization of low-power RTD/HBT digital ICs for high-speed transceivers-
dc.title.alternative초고속 Transceiver를 위한 저전력 공명 터널링 다이오드/이종접합 바이폴라 트랜지스터 디지털 회로의 설계 및 특성 분석-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN301331/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020025086-
dc.contributor.localauthorYang, Kyoung-hoon-
dc.contributor.localauthor양경훈-
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EE-Theses_Ph.D.(박사논문)
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