In this thesis, we are presented new direct-conversion architecture for the ATSC terrestrial digital TV tuner with a focus on the design of a highly linear low-noise amplifier and down-conversion mixer immune to device mismatch by process variations. Considering for the various tuner architectures, the direct-conversion architecture is chosen because of the advantage of low cost and easy single-chip integration.
A differential wide-band low-noise amplifier based on the current amplification scheme is proposed. In the low-noise amplifier, a common-gate stage with positive current feedback is integrated in parallel with a common-source stage using the current mirror amplifier in order to highly improve the linearity and exploit the noise cancellation technique. The proposed $0.18-\mu m CMOS LNA exhibits a power gain of 20.5 dB, an IIP3 of 2.7 dBm, an IIP2 of 43 dBm, and an average noise figure of 3.3 dB while consuming 32.4 mW from a power supply of 1.8 V with $0.12 mm^2$ area.
To remedy the harmonic-mixing problem which is the significant issue in the wide-band direct-conversion tuner, we are proposed a harmonic-suppression mixer consisted of the phase-shifting and gain-adjusting stage. The analysis for the limitation of harmonic-suppression in the presence of the phase and gain mismatch originated from process variations is performed. In order to minimize the effect of the device mismatch between the LO switches, a resistively degenerated double-balanced passive mixer along with a current feedback operational amplifier is employed, and thus we achieve high linearity and excellent device matching.
The prototype chip for the proposed direct-conversion architecture satisfying ATSC terrestrial digital TV system requirements is fabricated using a $0.18-\mu m$ single-poly six-metal RF CMOS technology. The proposed direct-conversion tuner is consisted of the highly linear low-noise amplifier, harmonic-suppression down-conversion mixer, and baseband programmable ...