Low latency encoder algorithm & reduced memory decoder architecture for non-binary turbo codes

Abstract

In this thesis, new encoder and decoder architectures are introduced that can greatly reduce the hardware complexity and computation time of non-binary turbo coding systems, without appreciable performance degradation. Since its introduction, turbo codes have been drawing truly remarkable interest not only from the coding theory community but also from all other areas of communication engineering. Now, turbo codes are widely considered as one of the major coding schemes for the future communication systems. In particular, non-binary turbo codes introduced recently are drawing growing attention from the coding theory community due to its excellent decoding convergence characteristics, large minimum distance, less susceptibility to the puncturing patterns, reduced latency, robustness to the decoding algorithm modifications and higher code rate. The major drawback of non-binary turbo codes is the exponential increase of the memory requirement for extrinsic information that can consume the major portions of the decoder area and power. In this thesis, a pseudo floating point representation method is proposed to significantly reduce the extrinsic memory requirement of non-binary turbo decoders without appreciable performance degradation. It is shown that 33~43% of the extrinsic information memory and as the result 13~18% of the total decoder complexity can be reduced in the case of the duo-binary turbo codes employed in the IEEE 802.16e standards. More dramatic complexity reduction is expected for the higher order non-binary turbo codes due to the exponential growth of the extrinsic memory size as the function of the symbol size order. Also an efficient tail biting algorithm is introduced that can speed up the tail biting process roughly by factor of two by judiciously exploiting the inherent structures of the IEEE 802.16e turbo encoders.