Systematic design space representation scheme for efficient exploration of ASIPASIP 설계 공간의 효과적인 탐색을 위한 설계 공간 표현 기법

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Modern digital systems design requires extensive exploration on the large and complex design space to find the best or a set of satisfiable configurations which meet design requirements. However, the forms of all the possible designs are so diverse that any single description has not yet been devised to express them all. Instead of expressing all the architectural design space, previous work used only parameterization method for design space representation. This approach provides simple description on the design space. On the other hand, it has a limitation that it can not express architectural variation. This thesis proposes a sound semantics for design space representation, with which a designer can express the architectural variation as well as parameterization. We extended the classical AND/OR graph to hold the characteristics of design space of digital system. The main goal of the representation is two folds: representation in formal semantics and expressive power of design alternatives. To meet such a goal, a formalism of attributed AND-OR graph is defined for design space representation. The AND and OR relations in the graph can represent not only a collection of components (AND relation) to form a system but also variants of alternatives (OR relation) to be used for a given component. Moreover, attributes attached at the vertex can represent ranges of parameters and constraints on selection of a set of alternatives located at different sub-modules. Constraints can be a good means to reflect many designers`` knowledge base. Based on Attributed AND/OR Graph, complete design space exploration framework is exemplified by introducing plan-generation-evaluation framework. The plan process implies the construction of a complete design space. Generation is a phase to synthesize a complete simulation model and evaluation is a step to measure the performance index of the generated models. Attributed AND/OR graph is utilized to implement the plan process. In addit...
Advisors
Kim, Tag-Gonresearcher김탁곤researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2006
Identifier
254399/325007  / 000995095
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2006.2, [ viii, 83 p. ]

Keywords

Hierarchical Pruning; Design Space Representation Scheme; Design Space Exploration; ASIP; 계층적 탐색; 설계 공간 표현 기법; 설계 공간 탐색 기법; Attributed AND/OR Graph

URI
http://hdl.handle.net/10203/35346
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=254399&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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