This dissertation has examined in detail a number of issues related to the integrated radio receivers particularly in the context of CMOS technologies. The techniques in this work have enabled the implementation of a low power high performance CMOS WLAN (IEEE802.11a & HiperLAN type 2) receiver front-end chipset for the direct conversion in a $0.18\mu m$ standard CMOS technology. This receiver front-end consumes less power and yields comparable or better performance with a higher of integration than most commercial receivers available today. This work demonstrates that the merge of CMOS technologies and the direct conversion receiver architecture is the most optimal choice to low cost, low power, and a high level of integration. In order to optimize RF performance in submicron CMOS process, this work investigates and optimizes the passive elements, such as the inductors and the varactors which are the key components in the VCO. The receiver including the integrated quadrature VCOs, the LNA, and the I/Q Mixers dissipates 48 mW (in maximum gain mode) from a 1.8 V supply, achieving a cascade noise figure of 5.3 dB, with -10 dBm IIP3. The QVCO used for LO generation, achieves a close-in phase noise of -115 dBc/Hz at an offset of 1 MHz with 1 GHz tuning range.
To overcome the well-known problem, such as DC offset, IQ mismatch, and 1/f noise of the direct conversion receiver, each block is designed to alleviate the discussed problems. All blocks are adopted differential topology as many as possible to suppress the common noise such as the substrate, the supply, and the coupling noise. The LNA has capability of controlling gains with following additional stage PGA. The purpose of the programmable gain amplifier (PGA) is to require the wide dynamic range and tenability of the system. This enhances the IIP3 by decreasing the gain at a high input-power level. It also provides a role as an active balun in case that single-ended input LNA is used for eliminating the burde...