DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kyung, Chong-Min | - |
dc.contributor.advisor | 경종민 | - |
dc.contributor.author | Yi, Ju-Hwan | - |
dc.contributor.author | 이주환 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2005 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=244911&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35286 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2005.2, [ xii, 109 p. ] | - |
dc.description.abstract | As the operational behavior of IC chips become more complex, the number of clocks in a single chip also increases. In particular, IP based designs drive the merging of heterogeneous modules into a single chip. Additionally, in the interest of reducing total energy usage, voltage and frequency scaling techniques are used to make such IPs operate at variable frequencies. Under such circumstances, designing interfaces for different clock connections becomes a highly complex task. In this thesis, a symbolic reachability analysis method and a model checking method for multiple-clock system designs are proposed. This is the first approach to deal with both synchronization problems caused by metastability and rate mismatch problems caused by clock frequency mismatches in a single framework. First of all, a method to remove certain parts of the design being verified is proposed. By removing certain parts of the design, we can reduce the complexity of the testbench model. Secondly, a method to remove one clock domain is proposed. This way, we can make a single clock model from multiple-clock models. Instead of setting inputs to the target model as free variables which could assume any arbitrary value regardless of the input constraints, the proposed method reflects the input constraints into the target model by modifying the transition relation of the target model. Therefore, false alarms caused by infeasible inputs do not occur. This was verified by various circuit examples. Two schemes are proposed to achieve this goal; one is to remove the testbench from the entire transition relation after removing the inactivated edges by applying a set of reachable states. The other is to apply the so-called input-sifting function to the transition relation of the target model to maximize the benefits of using a partitioned transition relation which is employed to deal with target systems of industrial complexity. Experimental results are given to show that an improvement in the m... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Asynchronous | - |
dc.subject | Model checking | - |
dc.subject | Formal verification | - |
dc.subject | Reachability analysis | - |
dc.subject | 상태 도달 분석 | - |
dc.subject | 비동기 | - |
dc.subject | 모델 확인 | - |
dc.subject | 형식 검증 | - |
dc.title | Reachability analysis and model checking technique for multiple-clock system verification | - |
dc.title.alternative | 다중 클락 시스템 검증을 위한 상태 도달성 분석 및 모델 확인 기술 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 244911/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000965311 | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.localauthor | 경종민 | - |
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