Quadrature direct digital frequency synthesis using fine-grain angle rotation

Abstract

A direct digital frequency synthesizer (DDFS) plays an important role in frequency agile communication systems due to its fast frequency switching, continuous phase, and good spectral performance. Spurious free dynamic range (SFDR) and power consumption are two important metrics used to evaluate DDFS performance. This thesis proposes a direct digital synthesis scheme that combines table lookup and single-step angle rotation to achieve both high SFDR and low power. The angle rotation is based on a new precise approximation. The proposed scheme consumes only 0.25mW/MHz to achieve 114-dBc SFDR, which is more than 40% reduced power compared to the state-of-the-art schemes. Angle rotation is widely used to synthesize digital frequency with high SFDR. The implementation is based on either successive approximation or complex multiplication. The former can use simple multiplierless computation units, but suffers from long latency and large internal bit-width required to reduce the accumulation of round-off errors. In contrast, the latter is free from the error accumulation, but requires many multipliers. To overcome the prior drawbacks, we introduce multiple starting points being effective in limiting the error accumulation, and propose a precise approximation that needs only two small multipliers to compute angle rotation for the fine phase. As an inverse operation of DDFS, the rectangular-to-polar coordinate converter is widely used in communication systems. Previous techniques have been developed based on the CORDIC algorithm and a modified angle rotation. Both of them require large amount of hardware in that datapath units having excessive internal bit resolution or many multipliers are necessary. To make the design compact, we propose a novel approach using truncated radix-4 SRT division technique. Targeting on the performance specification that has practical applications, the proposed approach confirms very efficient design in terms of hardware cost and output la...