DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Beom-Sup | - |
dc.contributor.advisor | 김범섭 | - |
dc.contributor.author | Kim, Jeong-Pyo | - |
dc.contributor.author | 김정표 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2004 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=240715&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35243 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2004.8, [ vii, 109 p. ] | - |
dc.description.abstract | This work focuses on the background calibration techniques for pipelined ADCs, which are represented by a random number sequence (RNS) based method and a skipand-fill method. Each of them has its own strength and weakness. The RNS-based method performs background operations in the true sense without any performance restriction but it takes a long time to accomplish whole calibration process. The skip-andfill method can effectively reconstruct skipped samples but it requires too large digital hardware to be implemented into on-chip. Firstly, a RNS-based background calibration technique is extended to the multi-stage calibration. It puts emphasis on correcting inter-stage residue gain errors mainly coming from capacitor mismatches and a finite op-amp DC gain. Proposed calibration process makes use. of comprehensive and effective methods such as a residue amplifier configuration with a tunable biased gain, a selective calibration scheme, and a block-LMS adaptation algorithm. This technique remarkably improves the ADC performance, especially when it is applied to multi-stage calibration. A prototype IC was fabricated in 0.18-㎛ CMOS technology. The designed ADC provides 10-bit resolution outputs with the SNDR of 55.3-dB and the SFDR of 62.6-dB. It works up to 80 MHz, dissipating 270-mW with a power supply of 1.8-V. Secondly, the conventional skip-and-fill method becomes more feasible by an LMS adaptive algorithm. By biasing the residue gain with a value greater than 2, calibrated pipelined stages provide extra bits of resolution after their calibration. These extra bits can be effectively used to compensate for the accumulated truncation error. An intensive foreground operation for error measurement shortens the initial setting of each calibration factor and the background skip-and-fill method periodically updates these factors. The skip-and-fill algorithm with an LMS adaptation shows comparable performance to conventional algorithms under various input conditions, ... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | Digital background calibration techniques for pipelined analog-to-digital converters | - |
dc.title.alternative | 파이프라인 아날로그 디지털 변환기를 위한 디지털 배경 보정 기법 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 240715/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000995090 | - |
dc.contributor.localauthor | Kim, Beom-Sup | - |
dc.contributor.localauthor | 김범섭 | - |
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