Inter-chip serial link design in CMOS

Abstract

In this work, high-speed inter-chip serial link transceiver is proposed. The four major blocks of transceiver, the transmitter, the receiver, clock generation and system interface are introduced. An input-multiplexing transmitter is implemented with small area and low power compared with output-multiplexing one. It shows only 5.04 ps (rms) jitter. To recover degraded signal by channel, adaptive equalization is used at the receiver front end. As an implementation of this adaptive equalizer, continuous time equalization with discrete time adaptation is adopted and sign-sign LMS algorithm is used. Realization of filter coefficient is done by charge pump and capacitor and this controls the gain of pre-amplifier. Accurate clock generation is the vital of multiplexing-demultiplexing of this transceiver. To achieve this requirement 4-phase clock generation, 4-stage self-biased differential delay cell oscillator structure is used. With an aid of high-frequency level shifter and symmetric Up/Dn current charge-pump, the PLL shows only 4.72ps (rms) jitter. Phase tracking type of clock-data recovery (CDR) circuit is implemented and new delay-immune CDR algorithm is proposed. New duty corrector that senses the output clock duty and feedback to its inverter chain is proposed. Finally, as a system work of 4-channel transceiver, 10Gbps Ethernet system interface is built. All these blocks are tested using customized graphical user interface based on PC with Windows OS. All this work is designed using standard 0.18㎛ $_1P6M$ CMOS process. Active area is 2.3mm by 2.3mm and consumes 178mW/ch. This transceiver achieves BER lower than ＜ $4.5x10^{-15}$.