DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Tag-Gon | - |
dc.contributor.advisor | 김탁곤 | - |
dc.contributor.author | Lee, Wan-Bok | - |
dc.contributor.author | 이완복 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2004 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=237650&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35220 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2004.2, [ ix, 106 p. ] | - |
dc.description.abstract | Systems design has been an iterative process which involves several steps such as modelling, logical analysis, performance evaluation and implementation. If each step requires different model, it would be a major hurdle to a seamless design process. Therefore a unified modelling framework which provides a basis to specify models at different steps in common semantics is desirable. In this thesis we propose a new composition-based verification methodology for the DEVS (Discrete EVent Systems specification) models. The suggested composition-based technique is applicable not only to the formal verification area but also to the area of simulation-based verification. Therefore it provides an axis of a unified framework based on the DEVS formalism. For the formal verification of discrete event systems we defined the CDEVS (Communicating Discrete Event Systems) formalism which is an extended version of the DEVS formalism providing the nondeterministic representation of a system. As a means of a systematic proof technique, two operations, namly composition and minimization, are defined. These operations are compatible with the meaning of the communication semantics of the DEVS models, thus they incorporate the feature of spontaneity of output events in an 10 (Input/Output) system. In our methodology, an implementation model is reduced to an observational equivalent model through a series of stepwise compositions and minimizations. This incremental approach alleviates the state explosion problem in a verification process. Once a final operational CDEVS model is obtained, it can be verified either by an equivalence checking algorithm or by a valid implementation relationship which investigates both the functional correctness and the timeliness property. The proposed approach is much promising when analyzing large systems. If a component should be changed due to a design error, the overall composed model can be rebuilt by just composing the changed model with the unchange... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | DISCRETE EVENT SYSTEMS | - |
dc.subject | DEVS | - |
dc.subject | VERIFICATION METHODOLOGY | - |
dc.subject | SIMULATION SPEEDUP | - |
dc.subject | 시뮬레이션 속도 개선 | - |
dc.subject | 모델 복합법 | - |
dc.subject | 이산사건 시스템 | - |
dc.subject | 검증방법론 | - |
dc.title | Composition-based verification methodology for discrete event systems | - |
dc.title.alternative | 모델 복합법을 이용한 이산사건 시스템의 검증방법론 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 237650/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000955282 | - |
dc.contributor.localauthor | Kim, Tag-Gon | - |
dc.contributor.localauthor | 김탁곤 | - |
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