Design of low power motion compensation (MC) and motion estimation (ME) hardware for portable video applications

Abstract

As the more multimedia applications are migrating from PC to the portable devices, the applications based on 2D image processing on portable devices will become important. When implementing them on portable devices, there are two critical constraints that must be considered together; the required performance and the power consumption. Especially, the power consumption is important factor in portable environments. For decoding, software solution is possible using current advanced embedded processors, but the power consumption becomes still high. For encoding, software-only solution is impossible due to its heavy computational complexity. Therefore, and hardware acceleration, especially for motion estimation (ME) and motion compensation (MC) is essential. In this research, hardware motion compensation (MC) accelerator is proposed to relieve the power consumption constraints for real-time video decoding in portable systems. It consists of two embedded frame buffers and the datapath for pixel processing. By embedding DRAMs as the frame buffers, the power consumption on data I/O transactions were dramatically reduced, and it also achieves good system performance with low clock frequency, 20MHz due to the wide I/O internal bus. In addition, the architecture of the frame buffer is optimized in terms of low power consumption, and various low power techniques such as distributed nine-tiled block mapping (DNTBM), sub-wordline scheme with partial activation control (PAC) has been adopted. By the above schemes, up to 31% of power reduction has been achieved compared with an ideal 1-bank memory structure. The prototype chip has been fabricated using 0.18㎛ embedded memory logic (EML) technology. 1.125Mbit DRAM and logic for pixel processing is integrated to support MPEG-4@L1 bitstream, and the overall block consumes about 16mW. In addition to MC accelerator, a low power ME accelerator is proposed. It is based on the hierarchical algorithm, and its internal memory requireme...