DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Shin, Hyung-Cheol | - |
dc.contributor.advisor | 신형철 | - |
dc.contributor.author | Han, Sang-Yeon | - |
dc.contributor.author | 한상연 | - |
dc.date.accessioned | 2011-12-14 | - |
dc.date.available | 2011-12-14 | - |
dc.date.issued | 2003 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=231143&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/35192 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ v, 161 p. ] | - |
dc.description.abstract | In this dissertation, a new bulk MOSFET structure, which can be used for 50 nm regime and beyond, has been proposed. Due to n+ floating polysilicon spacers (FPS) at both sides of the $p^+$ main gate, inversion layers are induced below the FPS. Since the extended S/D regions are electrically induced, this junction is extremely shallow and effectively suppresses short channel effect (SCE). In order to fabricate the proposed device structure for sub-50 nm regime, two key process techniques were needed. The one is the sub-50 nm lithography technology and the other is ultrathin oxide on $p^+$ polysilicon layer. Sub-50 nm lithography technology was obtained using E-beam lithography system and SAL601 negative type E-beam resist. Specifically, 40nm electron beam lithography was developed. And ultrathin oxide between $p^+$ polysilicon and $n^+$ polysilicon was realized by ECR $N_2O$ plasma oxidation. Sub-4 nm ECR $N_2O$ plasma oxide on $n^+/p^+$ polysilicon layer were fabricated and characterized. These oxides have relatively larger breakdown field and smaller electron trapping behaviors than that of thermal polyoxides. Using these processes, a new bulk 50 nm MOSFET with $p^+$ poly-Si main-gate and $n^+$ poly-Si spacers has been proposed and fabricated. Due to $n^+$ floating polysilicon spacers (FPS) at both sides of the $p^+$ poly-Si main-gate, inversion layers acting as extended S/D are induced under the FPSs. We have got the reasonable IV characteristics, and obtained $I_{on}=460μA/μm$ at $V_{GS}-V_{TH}=1.5V$ and $V_{DS}=1.5V$. We investigated the operation of the spacer-gate MOSFET and verified that the inversion layer was formed under the $n^+$ poly-Si spacers. For further reduction of the gate channel length, we adopted the oxide trimming technique using 50 nm E-beam lithography technology. 20 nm polysilicon patterning technology is developed using 50 nm E-beam lithography, oxide trimming technique, and gate polysilicon dry etch. Using these proces... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | extended source/drain | - |
dc.subject | coupling ratio | - |
dc.subject | capacitive coupling | - |
dc.subject | 50 nm MOSFETs | - |
dc.subject | floating sidegate | - |
dc.subject | 부유 옆게이트 | - |
dc.subject | 확장 소스/드레인 | - |
dc.subject | 커플링 비율 | - |
dc.subject | 커패시티브 커플링 | - |
dc.subject | 50 nm 금속 산화 반도체 전계효과 트랜지스터 | - |
dc.title | (A) study on sub 50-nm MOSFET with floating polysilicon spacers | - |
dc.title.alternative | 부유 다결정 실리콘 스페이서를 이용한 50 nm 이하급 MOSFET에 관한 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 231143/325007 | - |
dc.description.department | 한국과학기술원 : 전기및전자공학전공, | - |
dc.identifier.uid | 000975414 | - |
dc.contributor.localauthor | Shin, Hyung-Cheol | - |
dc.contributor.localauthor | 신형철 | - |
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