(A) study on sub 50-nm MOSFET with floating polysilicon spacers

Abstract

In this dissertation, a new bulk MOSFET structure, which can be used for 50 nm regime and beyond, has been proposed. Due to n+ floating polysilicon spacers (FPS) at both sides of the $p^+$ main gate, inversion layers are induced below the FPS. Since the extended S/D regions are electrically induced, this junction is extremely shallow and effectively suppresses short channel effect (SCE). In order to fabricate the proposed device structure for sub-50 nm regime, two key process techniques were needed. The one is the sub-50 nm lithography technology and the other is ultrathin oxide on $p^+$ polysilicon layer. Sub-50 nm lithography technology was obtained using E-beam lithography system and SAL601 negative type E-beam resist. Specifically, 40nm electron beam lithography was developed. And ultrathin oxide between $p^+$ polysilicon and $n^+$ polysilicon was realized by ECR $N_2O$ plasma oxidation. Sub-4 nm ECR $N_2O$ plasma oxide on $n^+/p^+$ polysilicon layer were fabricated and characterized. These oxides have relatively larger breakdown field and smaller electron trapping behaviors than that of thermal polyoxides. Using these processes, a new bulk 50 nm MOSFET with $p^+$ poly-Si main-gate and $n^+$ poly-Si spacers has been proposed and fabricated. Due to $n^+$ floating polysilicon spacers (FPS) at both sides of the $p^+$ poly-Si main-gate, inversion layers acting as extended S/D are induced under the FPSs. We have got the reasonable IV characteristics, and obtained $I_{on}=460μA/μm$ at $V_{GS}-V_{TH}=1.5V$ and $V_{DS}=1.5V$. We investigated the operation of the spacer-gate MOSFET and verified that the inversion layer was formed under the $n^+$ poly-Si spacers. For further reduction of the gate channel length, we adopted the oxide trimming technique using 50 nm E-beam lithography technology. 20 nm polysilicon patterning technology is developed using 50 nm E-beam lithography, oxide trimming technique, and gate polysilicon dry etch. Using these proces...