High-speed serial communication using half-frequency clock

Abstract

This paper describes a simplified structure of serial link using voltage controlled delay line. The circuit is designed on top of the mesochronous timing scheme that a transmitter and a receiver share the same reference clock source. By virtue of specially devised simple phase detector named “overlapped transition PD”, the hardware can be saved a lot and a half-frequency clock that compensates for the speed impairment of CMOS devices can be used in recovering the serial stream data. In addition, the processing delay involved in detecting the data transition edges is so small compared to the conventional detection schemes that stability issues typically occurring in the phase correction loop can easily be figured out. Also since the proposed PD performs the charge pump operation together, a minimized design complexity and easy design strategy can be promised. And a dual loop structure of the incorporated digital DLL improves the two core features of locking time and low jitter simultaneously, which are always conflicting in most architectures. A test-chip is fabricated to demonstrate the functionality of newly proposed scheme and incorporated recovery loop with gigahertz rate bit streams. A 0.18um 1P6M CMOS process and PBGA package for low pad parasitics were used. A proto-chip works properly up to 3.125 [Gbps] NRZ data rate at the expense of a little high-frequency internal circuit operation.