(A) feature-assisted search algorithm and area-efficient VLSI architecture for fast motion estimation고속 움직임 추정을 위한 특징 기반 탐색 알고리즘 및 소면적 VLSI 구조

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Video compression plays an important role in transmission and storage of digital video data. The main idea to achieve compression is to remove temporal and spatial redundancies existing in video sequences. One effective method commonly used in reducing temporal redundancy is motion-compensated predictive coding. The essential part in motion-compensated coding is motion estimation. Block matching algorithm (BMA) has been widely used as a motion estimation technique in most video coding systems due to its simplicity. Its goal is to find a block that is most similar to a current block within a pre-defined search area in the previous frame. As a straightforward method, the full search BMA (FSBMA) is widely used because of its high performance and low control overhead. Usually, FSBMA is the most time consuming part in a video encoder. This heavy computational load limits the performance of encoder in terms of encoding speed and power consumption. Meanwhile, many VLSI architectures for FSBMA have been reported previously. However, due to their high computational complexity, VLSI architectures for FSBMA usually require a large number of gates and high memory bandwidth for real time applications. In order to reduce the heavy computational load of FSBMA, active research has been focused on fast BMAs for a long time. A software solution is attractive from the viewpoint of cost effectiveness and flexibility. In software implementation for real time applications, a gradient descent approach is a good candidate due to its high speed up improvement compared to other approaches. In the other side, hardware implementation of motion estimation is also important for portable multimedia devices. In this case, to reduce manufacturing costs, such as silicon size and I/O bandwidth, a low complexity BMA suitable for hardware implementation and corresponding efficient VLSI architecture are also necessary. In hardware implementation, a multi-resolution approach is a good candidate due ...
Advisors
Ra, Jong-Beomresearcher나종범researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2003
Identifier
181159/325007 / 000985280
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ vii, 100 p. ]

Keywords

Selective integral projection; Feature matching; Motion estimation; Block matching; VLSI architecture; VLSI 구조; 선택적 가산 투영; 특징 정합; 움직임 추정; 블록 정합

URI
http://hdl.handle.net/10203/35146
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=181159&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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