Grid-based ray tracing on the cell processor

Abstract

As the clock rate for the single-core architectures increases, power efficiency and wire delay become new problems for the performance limitation. To solve these problems, the multi-core architectures are issued. One of them is $\it{Cell Broadband Engine Architecture}$ (or Cell Processor), which was developed by Sony, Toshiba, and IBM(as known as STI), has a general purpose Power Processing Element(PPE) and 8 Synergistic Processing Elements(SPE). The Cell Processor achieves high performance on vector processing and multimedia applications due to the simple design. On the other side of the great performance, the Cell Processor has many disadvantages in that there is no cache, nor branch predictor, and it has a distributed memory system. We expect that Ray Tracing, one of the most common rendering algorithm, shows good performance on the Cell Processor, because it is known as typical parallel application. There are many acceleration structures for ray tracing. One of them is the grid structure, which is simple but commonly known as slow algorithm. However, recently grid traversal algorithms are improved, and its performance is comparable with kd-tree structure which is one of the fastest acceleration structure. In this paper, we introduce an implementation of the parallel ray tracer on the Cell Processor using grid structure. We think the grid structure is good for the Cell Processor, because only the grid structure is not hierarchical. Using the grid structure, we can predict next data and apply double buffering for DMA latency hiding. Also, the grid structure allows us sequential memory access, so we use macrocell, a set of grid cells, to compute. We show that the grid-based ray tracer has many potentials on the Cell Processor.