Write performance improvement for multi-chip based NAND flash storage system

Abstract

NAND flash memory is in the limelight as a new storage medium due to the advantages such as low power consumption, fast random access time, and shock resistance. Multi-chip architecture that uses many flash chips is universal because of the limitation of capacity and performance. However, the previous researches are mainly about increasing cache hit ratio of buffer cache or performance improvement of buffer cache which uses a single flash chip. Thus, researches for multi-chip architecture are needed. We analyze the effect of read-modify-write operation, which occurs because the request unit of host system and the request unit of flash memory are different. We also propose a replacement algorithm giving consideration to multi-chip, called MCA. The MCA is an algorithm which alleviates the problem of read-modify-write operation by rescheduling the victim pages in buffer cache. Our simulation results show that MCA outperform other buffer cache schemes up to 20% as the chip idle time is minimized.