In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. As a result, many researchers investigated various techniques to reduce the memory latency. One way to improve memory latency is exploiting localities built in applications. Modern micro-processors usually adapt cache to exploit those localities. In this paper, we propose enhanced field remapping techniques for dynamically allocated structures to provide better locality than conventional field layouts can. By aggregating and grouping fields from multiple structures, we restructure the layout of fields in dynamic structures, reducing cache miss rates, amount of page usages, and execution time as a result. Experimental results with Olden benchmark show the effectiveness of our field remapping approaches. Compared to the original programs, average L1 and L2 cache misses are reduced by 30% and 10%, respectively. As a result, our remapping achieves 13% faster execution time on average than original programs. These results are far better than previously proposed field remapping methods, which require wasted padding between fields when the sizes of fields are different.