Synthesis of arithmetic circuits considering leakage power minimization

Abstract

In deep submicron (DSM) design, the interconnect delay and leakage power becomes equally as or more important than logic gates delay and dynamic power. In particular, to achieve good synthesis result in DSM design, it is essential to consider the interconnect delay and leakage power at an early stage of the synthesis process. Unfortunately, few successes of achieving a tight link of front-end synthesis to back-end layout have been reported, in a practical point of view, mainly due to the inaccuracy of predicting the layout effects during the synthesis. In this thesis, we address a new approach to the problem of synthesis of arithmetic circuits combined with the consideration of layout effects and leakage power minimization to overcome some of the limitations of the previous works, in which the effects of layout on the synthesis have never been taken into account or considered in local and limited ways, or whose computation time is extremely large. Our leakage power optimization is based on the use of dual-threshold voltage($V_t$) technology. The proposed approach performs in two phases. In phase 1, an iterative timing-driven synthesis and placement technique is applied to an arithmetic expression using FA/HA cells with high-$V_t$(i.e., slower but lower leakage power than that of low-$V_t$). This iterative mechanism practically tightly integrates the synthesis and placement tasks so that both of the effects of placement on the results of synthesis and the effects of synthesis on the results of placement are fully and effectively taken into account. This phase produces a synthesis and placement result with the least leakage power consumption. In Phase 2, A technique of minimally replacing the FA/HA cells with high-$V_t$ from the result in phase 1 by FA/HA cells with low-$V_t$ (i.e., more leakage power but faster than that of high-$V_t$) to meet the timing constraint of circuit. From experiments using a set of benchmark designs, it is shown that the approach is q...