(A) study on bus synthesis for low power in VLSI systen design

Abstract

Bus is one of the most design components to be optimzied in VLSI design, particularry in terms of power consumption. This thesis addresses two problems in bus synthesis for low power: (1) Bus encoding and (2) Bus scheduling/binding. For (1), we improve the bus-invert encoding technique to further reduce the total number of data transitions on buses. The idea is, unlike the existing schemes in which the entire or one subset of the bus lines are considered for bus-invert coding, to partition the bus lines according to the transition patterns of data values, and apply the coding scheme to each of them independently. For (2), we propose an integrated bus scheduling and binding algorithm based on network flow method. This leads us not only to find a theoritically solid solution of bus synthesis for low power but also to fully exploit the effect of scheduling on bus binding. Experimental data using a set of benchmark examples are provided to show the effectiveness of the proposed algorithms in reducing power consumption on the bus.