Multiplexor-tree optimization in high level synthesis for VLSI design

Abstract

This thesis addresses the allocation problem of multiplexors in High-level synthesis in VLSI(Very Large Scaled Integrated)design. One main optimization task in HLS is resource sharing among the operations to minimize the required amount of hardware under the clock time budget constraint. However, the resource sharing invariably introduces multiplexors at the inputs of functional units. Consequently,the delay and area by the multiplexors also becomes a non-trivial factor in terms of circuit timing and area. This thesis focuses on the optimization of multiplexors. Specifically, the key contribution is that we introduce a new concept of optimizing multiplexor trees across clock steps and proposed an efficient multiplexor-tree partitioning algorithm. From experiments with a set of HLS benchmark examples, the proposed approach is able to reduce the circuit area by 18.3% on average under the same clock time constraint when compared to those by produced the conventional multiplexor tree allocation.