(A) proposal for formal scheme in AND parallel execution of logic programs

Abstract

In this thesis, we treat of AND parallel execution of logic programs, especially, backtracking and resetting. As a means to overcome difficulty in understanding AND parallel execution of logic programs, a formal framework for AND parallel execution is proposed. The proposed framework can give a rather formal view to AND parallel execution of logic programs than that of algorithmic presentation. Based on the proposed formal framework, an intelligent scheme for backtracking and resetting is proposed. For more intelligent backtracking, an analysis, called literal failure analysis, can be applied optionally. The proposed intelligent resetting scheme is based on the binding information of each failed literal, which its a main origin of intelligent resetting. Correctness of the proposed resetting scheme is proved in a simple and formal way. The proposed scheme is simulated with a parallel simulator and experimental results are also given in comparison with other research.