DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Cho, Jung-Wan | - |
dc.contributor.advisor | 조정완 | - |
dc.contributor.author | Lee, Yun-Sik | - |
dc.contributor.author | 이윤식 | - |
dc.date.accessioned | 2011-12-13T05:48:38Z | - |
dc.date.available | 2011-12-13T05:48:38Z | - |
dc.date.issued | 1983 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=63746&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/33570 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전산학과, 1983.2, [ [i], 49, [1] p. ] | - |
dc.description.abstract | This thesis suggests an indispensible and basic tools for design automation of a digital system and its design verification. It translates description of the digital system expressed by the hardware description language into a computer executable codes like polish strings or Boolean equations, or logic diagrams. DDL, which is a more hardware oriented language among hardware description languages, is used to describe system components. Finally, this thesis produces a logic diagram which is a gap to be bridged in the design automation area. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | Design automation process using hardware description language | - |
dc.title.alternative | Hardware description language 를 이용한 설계의 자동화 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 63746/325007 | - |
dc.description.department | 한국과학기술원 : 전산학과, | - |
dc.identifier.uid | 000811202 | - |
dc.contributor.localauthor | Cho, Jung-Wan | - |
dc.contributor.localauthor | 조정완 | - |
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