(An) emulation oriented dynamic microprogrammable processor design

Abstract

This thesis proposes an architecture of emulation oriented processor. The target machine attributes which have impact on emulation efficiency are studied briefly. From this study, we have noticed that the indispensable features of Dynamic Microprogrammable Processor (DMP) organization are flexible field manipulation, residual control, microinstruction as parameterized template and flexible control structure. With the above concepts in mind, we have designed an efficient DMP. In the DMP, FMU (Field Manipulation Unit), SUR (Set Up Register), and RP (GPR-pointer register) emulate the functions of the various target machine general purpose registers cooperatively. By writing microcodes for DMP to emulate a number of IBM 370 machine instructions and by walking through them, performance is estimated.