Fault diagnosis of bit-sliced processors

Abstract

This thesis proposes a microdiagnostic methodology for efficient fault diagnosis of bit-sliced processors that are formed by an array of many identical bitslice processors. Test generation methodology for testing the entire array simultaneously instead of testing single slice one after another is presented, which is based on high functional fault model, restricted multiple fault-slice assumption within an array. Fault detection and fault location methodologies using the derived test sequence are also presented. Using these methodologies, a test microprogram and a diagnostic system for the bit-sliced processor formed by the array of four Am2901 bit-slice processors are developed.