Energy efficient front-end architecture for next generation microprocessors

Abstract

Mordern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increse the complexity and power consumption. In this dissertation, we propose low power and high performance techniques for contemporary microprocessors. First, the small reorder buffer(SROB) reduces power consumption by deferred allocation and early release. The deferred allocation delayes the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Third, in order to achieve high performance, we propose a fast and low-cost branch recovery technique using the incremental register renaming (IRR) and the bit-vector based rename map table (BVMT). The IRR enforces the destination register number of the instruction stream to appear in non-decreasing order. With this incremental property of the IRR, the BVMT recovery scheme completely eliminates the roll-back overhead on branch misprediction. Thus, the instruction fetcher does not stop and it fetches instructions from the correct path immediately after the misprediction detected. Experimental results show that our proposed designs reduce power dissipation and achieve high performance by an average of 24.45% and 1...